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W25Q80BW
7.2.38
Read Security Registers (48h)
The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data
bytes to be sequentially read from one of the four security registers. The instruction is initiated by driving
the /CS pin low and then shifting the instruction code “48h” followed by a 24 -bit address (A23-A0) and
eight “dummy” clocks into the DI pin. The code and address bits are latched on the rising edge of the CLK
pin. After the address is received, the data byte of the addressed memory location will be shifted out on
the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is
automatically incremented to the next byte address after each byte of data is shifted out. Once the byte
address reaches the last byte of the register (byte FFh), it will reset to 00h, the first byte of the register,
and continue to increment. The instruction is completed by driving /CS high. The Read Security Register
instruction sequence is shown in figure 36. If a Read Security Register instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Security Register instruction allows clock rates from D.C. to a
maximum of F R (see AC Electrical Characteristics).
ADDRESS
Security Register #0*
Security Register #1
Security Register #2
Security Register #3
A23-16
00h
00h
00h
00h
A15-12
0000
0001
0010
0011
A11-8
0000
0000
0000
0000
A7-0
Byte Address
Byte Address
Byte Address
Byte Address
* Please note that Security Register 0 is Reserved by Winbond for future use. It is
recommended to use Security registers 1- 3 before using register 0.
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
CLK
Mode 0
Instruction (48h)
24-Bit Address
DI
(IO 0 )
23
*
22
21
3
2
1
0
DO
(IO 1 )
/CS
* = MSB
High Impedance
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
CLK
Dummy Byte
DI
(IO 0 )
0
7
6
5
4
3
2
1
0
Data Out 1
Data Out 2
DO
(IO 1 )
High Impedance
7
*
6
5
4
3
2
1
0
7
*
6
5
4
3
2
1
0
7
Figure 36. Read Security Registers Instruction Sequence
Publication Release Date: July 30, 2013
- 57 -
Revision J
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